The present invention relates generally to integrated circuits and the like, and more particularly to a system that uses body-biased sleep transistors to reduce leakage power and to minimize performance penalties and noise in integrated circuits and the like.
Ever increasing performance demands are being placed on computer circuits, microprocessors, application specific integrated circuits (ASICs) and other ICs and VLSICs. ASICs, ICs and VLSICs are being required to operate at continually increasing clock speeds to perform more operations in a shorter period of time. To provide these faster operating speeds, circuits and processes are being designed to operate at lower threshold voltages. With the lower threshold voltages, the flow of leakage current from a system power supply to a circuit supplied by the system power supply can increase. The leakage current can therefore result in a significant amount of power consumption in a circuit. This can be critical in mobile, battery powered electronic devices, such as cellular telephones, mobile radios, laptop computers and handheld computing devices and the like, where the ability to operate for extended periods of time on battery power is of primary importance to users.
One arrangement for reducing leakage current and power consumption in a circuit is through the use of sleep transistors that can have either high or low threshold voltages. This arrangement is described in U.S. patent application Ser. No. 09/151,827 by Ye et al., file Sep. 11, 1998 and entitled xe2x80x9cA Method and Apparatus for Reducing Standby Leakage Current Using a Leakage Control Transistor That Receives Boosted Gate Drive During an Active Modexe2x80x9d and assigned to the same assignee as the present application. When the sleep transistor is active or turned on, the system power supply is supplying current to the circuit. When the sleep transistor is idle or turned off, the intent is that no current is supplied to the circuit. However, depending upon the characteristics of the sleep transistor and the circuit or load, there will be some leakage current through the sleep transistor and power consumption in the circuit. There will be some voltage drop across the sleep transistor and the circuit effectively has a Air small voltage supply that can cause a performance penalty in terms of operational delays and noise interference. The magnitude of this performance penalty, as well as the degree of leakage power reduction will depend upon the size and operating characteristics of the sleep transistor. Larger sleep transistors typically provide a smaller leakage reduction factor but also a smaller impact on performance. In other words, there is a trade-off between performance impact and leakage reduction. Large sleep transistors minimize the performance impact, but take up a larger amount of area and do not provide as much leakage reduction. Smaller sleep transistors reduce leakage by a larger amount or factor but also suffer some impact to performance.
Accordingly, for all of the reasons discussed above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for a system and method to reduce leakage current and power consumption in a circuit on an IC or other electronic device while minimizing the impact on performance and the generation of noise that can adversely affect the operation of the circuit or other components on the IC.